Semiconductor fabrication generally uses photoresist in etching and other processing steps. In the etching steps, a photoresist masks areas of the semiconductor substrate that are not etched. Examples of the other processing steps include using a photoresist to mask areas of a semiconductor substrate in an ion implantation step or using the photoresist as a blanket protective coating of a processed wafer or using the photoresist as a blanket protective coating of a MEMS (micro electro-mechanical system) device.
State of the art integrated circuits can contain up to 6 million transistors and more than 800 meters of wiring. There is a constant push to increase the number of transistors on wafer-based integrated circuits. As the number of transistors is increased there is a need to reduce the cross-talk between the closely packed wire in order to maintain high performance requirements. The semiconductor industry is continuously looking for new processes and new materials that can help improve the performance of wafer-based integrated circuits.
Materials exhibiting low dielectric constants of between 3.5-2.5 are generally referred to as low-k materials and porous materials with dielectric constant of 2.5 and below are generally referred to as ultra low-k (ULK) materials. For the purpose of this application low-k materials refer to both low-k and ultra low-k materials. Low-k materials have been shown to reduce cross-talk and provide a transition into the fabrication of even smaller integrated circuit geometries. Low-k materials have also proven useful for low temperature processing. For example, spin-on-glass materials (SOG) and polymers can be coated onto a substrate and treated or cured with relatively low temperature to make porous silicon oxide-based low-k layers. Silicon oxide-based herein does not strictly refer silicon-oxide materials. In fact there are a number of low-k materials which have silicon oxide and hydrocarbon components and/or carbon, wherein the formula is SiOxCxHz, referred to herein as hybrid materials and designated herein as MSQ materials. It is noted, however, that MSQ is often designated to mean Methyl Silsesquioxane, which is an example of the hybrid low-k materials described above. Some low-k materials such as carbon doped oxide (COD) or fluoridated silicon glass (FSG), are deposited using chemical vapor deposition techniques, while other low-k materials, such as MSQ, porous-MSQ, and porous silica, are deposited using a spin-on process.
While low-k materials are promising materials for fabrication of advanced micro circuitry, they also provide several challenges they tend be less robust that more traditional dielectric layer and can be damaged by etch and plasma ashing process generally used in pattern dielectric layer in wafer processing, especially in the case of the hybrid low-k materials, such as described above. Further, silicon oxide-based low-k materials tend to be highly reactive after patterning steps. The hydrophillic surface of the silicon oxide-based low-k material can readily absorb water and/or react with other vapors and/or process contaminants which can alter the electrical properties of the dielectric layer itself and/or diminish the ability to further process the wafer.
What is needed is a method of passivating a low-k layer especially after a patterning steps. Preferably, the method of passivating the low-k layer is compatible with other wafer processing steps, such as processing steps for removing contaminants and/or post-etch residue after a patterning step.